Designs of electronics and computing devices have become increasingly concentrated on power conservation in order to improve performance in areas including battery life or heat emission. One area in conserving power is by reducing the amount of current leakage occurring within a circuit. Electrical circuits inherently have current leakage through different components. For example, in digital logic, each gate leaks some amount of current over time. Higher leakage means higher power consumption. One circuit state for reducing leakage current is standby or sleep state, wherein a circuit is not in use but may be in use at a later time. Therefore, a sleep state allows the circuit to conserve power by freezing active operation of the circuit (e.g., active switching of multiple components) and waiting to be placed from the sleep state into a non-sleep state. Hence, values currently existing in the circuit may be preserved in the sleep state until the circuit is brought out of the sleep state. As a result, values are not loaded into or recomputed by the circuit because the values already exist in the circuit when brought out of the non-sleep state.
The advantage of a sleep state over powering off the circuit is that the circuit is more easily brought into a non-sleep state from a sleep state over initializing the circuit. In initialization, a circuit loads or computes the values that would have been stored in a sleep state. Therefore, time and power is lost during initialization. But when a circuit is in a sleep state, current may leak from the components of the circuit as power may still be applied to them. Therefore, leakage current still exists in the circuit during a sleep state.
In one approach, the overall leakage current may be reduced by placing different nodes of the circuit at predetermined logic values during a sleep state. For example, a logic one at a node of the circuit may have a lower leakage current than the circuit with a logic zero at the node. Again, though, the values of certain nodes in the circuit are to be preserved while forcing other various nodes of the circuit to a logic value.
In one implementation to the approach, a logic AND gate is inserted at each of the predefined nodes with an input that is lowered to a logic zero when the circuit is to enter a sleep state. Therefore, the predefined node is split so that the input to the AND gate preserves a value while the output from the AND gate forces the node to a predetermined logic value. In addition, a number of AND gates equal to the number of nodes is added to the circuit, thus adding more logic to the circuit. One problem with the implementation is that the inserted gate itself is leaky. In addition to increasing the circuit size and degrading the circuit timing, the inserted gate may substantially increase power consumption.
In another implementation, existing logic gates are modified in order to add a transistor in series with the pull up stack of the gate and another transistor in parallel with the pull down stack, or vice-versa. Hence, the transistors allow the output of the gate to be forced to a logic one or a logic zero. Problems, though, are that conventional cell libraries may not be used and the modified gates are slower and require more area. In another implementation, a preexisting scan chain of a circuit is used in order to scan in a predefined output vector into the latches of the circuit, thereby forcing the outputs of the latches to specific values. One problem with the implementation is that scanning in a vector takes multiple steps of switching latches. Thus, scanning the vector into the chain takes time and drains power.